1. Field of the Invention
The present invention relates to techniques for routing signals across a semiconductor chip. More specifically, the present invention relates to a method and an apparatus for routing differential signals across a semiconductor chip in a manner that reduces effective capacitance and differential coupling.
2. Related Art
As processor clock speeds continue to increase at an exponential rate, data must be transferred at correspondingly faster rates between computer system components. This can be a problem for conventional bus structures because the faster switching speeds and smaller voltage swings in the latest generation of semiconductor chips cause signal lines to be more sensitive to noise.
To remedy this problem, designers are beginning to use differential signaling to transmit signals across a semiconductor chip. Differential signaling uses two signal lines to carry a “true” and “complement” version of each signal, wherein the value of the signal is indicated by the voltage difference between the two signal lines. Because currents are balanced between power and ground rails, differential signaling reduces power supply noise and effectively provides return currents. Moreover, differential signaling is less sensitive to ground shifts (or other common mode noise) between sender and receiver because differential signaling relies on voltage differences between pairs of signal lines, instead of relying on an absolute voltage level of a single signal line.
As the demand for higher bandwidth continues to increase, designers are beginning to pack differential wires tightly together to increase the total number of communication channels. However, when differential wires are packed tightly together, they can potentially interfere with each other through energy coupling, which can have deleterious effects on performance and reliability. For example, FIG. 1 illustrates a differential pair of wires, A and Ā, which carry complementary signals. Hence, if A moves up, Ā moves down, and vice versa. The differential pair, B and {overscore (B)}, operates in the same manner. Note that these differential pairs typically belong to a wider signal bus, which includes additional differential pairs of the same length that run in the same direction.
In the arrangement of wires as illustrated in FIG. 1, signals in neighboring wires can potentially interfere with each other. For example, if a signal in wire B moves up, the corresponding complement signal in wire {overscore (B)} moves down. Since wire Ā is adjacent to wire B, this can couple energy into wire Ā, which can potentially cause errors or reduce performance. Furthermore, note that signals in wires Ā and B can disturb each along the entire length of the wires.
In order to remedy this problem, designers sometimes “twist” differential pairs of wires. For example, FIG. 2 illustrates a “fully-twisted” wiring scheme. In this fully-twisted scheme, if wire B moves up, it couples wire Ā upwards for ¼ of the wire length, but it also couples wire A upwards for ¼ of the wire length. At the same time, wire Ā has the same downward effect on both B and {overscore (B)}. Hence, the net coupling effect is zero in the first order.
Note, however, that wires A and Ā (and wires B and {overscore (B)}) are adjacent, and typically with minimal spacing. The line-to-line capacitance of two adjacent wires in a modem technology is approximately 70% of the total capacitance of the wire. In addition, the effective capacitance between any two physical structures doubles when the voltage on those two structures swings in opposite directions. Consequently, this fully-twisted scheme doubles the wire-to-wire “effective” capacitance seen by each wire, thereby causing higher power dissipation as well as longer delay.
Hence, what is needed is a method and an apparatus for routing differential signals across a semiconductor chip in a manner that reduces effective capacitance as well as differential coupling.